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functional block diagram voiceband analog input a voiceband analog input b differential analog output digital data and control serial port 16-bit sigma- delta dac 16-bit sigma- delta adc mux +20db amp voltage reference pga rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a voiceband signal port one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 ad28msp02 features complete analog i/o port for voiceband dsp applications linear-coded 16-bit sigma-delta adc linear-coded 16-bit sigma-delta dac on-chip anti-aliasing and anti-lmaging filters on-chip voltage reference 8 khz sampling frequency twos complement coding 65 db snr + thd programmable gain on dac and adc serial interface to dsp processors 24-pin dlp/28-lead soic single 5 v power supply general description the ad28msp02 voiceband signal port is a complete analog front end for high performance voiceband dsp applications. compared to traditional m -law and a-law codecs, the ad28msp02s linear-coded adc and dac maintain wide dynamic range while maintaining superior snr and thd. a sampling rate of 8.0 khz coupled with 65 db snr + thd per- formance make the ad28msp02 attractive in many telecom and speech processing applications, for example digital cellular radio and high quality telephones. the ad28msp02 simplifies overall system design by requiring only a single +5 v power supply. the inclusion of on-chip anti-aliasing and anti-imaging filters, 16-bit sigma-delta adc and dac, and programmable gain amplifiers ensures a highly integrated and compact solution to voiceband analog processing requirements. sigma-delta conver- sion technology eliminates the need for complex off-chip anti- aliasing filters and sample-and-hold circuitry. the ad28msp02s serial i/o port provides an easy interface to host dsp microprocessors s uch as the adsp-2101, ads p-2105 and adsp-2111. the ad28msp02 is available in a 24-pin, 0.3" plastic dip and a 28-lead soic package. functional description figure 1 shows a block diagram of the ad28msp02. a/d conversion the a/d conversion circuitry of the ad28msp02 consists of two analog input amplifiers, an optional 20 db preamplifier, and a sigma-delta analog-to-digital co nverter (adc). the analog input signal to the ad28msp02 must be ac-coupled. analog input amplifiers the two analog input amplifiers (norm, aux) are internally biased by an on-chip voltage reference in order to allow opera- tion of the ad28msp02 with a single +5 v power supply. an analog multiplexer selects either the norm or aux ampli- fier as the input to the adcs sigma-delta modulator. the optional 20 db preamplifier may be used to increase the signal level; the preamplifier can be inserted before the modulator or can be bypassed. input signal level to the sigma-delta modulator should not exceed v inmax , which is specified under analog interface electrical characteristics. refer to analog input in the design considerations section of this data sheet for more information. the input multiplexer and 20 db preamplifier are configured by bits 0 and 1 (ips, ims) of the ad28msp02s control register. if the multiplexer setting is changed while an input signal is being processed, the adcs output must be allowed time to settle to ensure that the output data is valid. adc the adc consists of a 2nd-order analog sigma-delta modulator, an anti-aliasing decimation filter, and a digital high-pass filter. the sigma-delta modulator noise-shapes the signal and pro- duces 1-bit samples at a 1.0 mhz rate. this bit stream, which represents the analog input signal, is fed to the anti-aliasing decimation filter. decimation filter the anti-aliasing decimation filter contains two stages. the first stage is a sinc 4 digital filter that increases resolution to 16 bits and reduces the sample rate to 40 khz. the second stage is an iir low-pass filter.
ad28msp02 rev. 0 C2C output differential amp control register voltage reference 1 16 16 input amp analog sigma-delta modulator 1.0 mhz anti-aliasing decimation filter digital high-pass filter 8.0 khz 8.0 khz 16-bit sigma-delta adc vfb norm vin norm 16 8.0 khz sdi sdifs sdo sdofs sclk data/ cntrl mux input amp vfb aux vin aux +20db amp norm aux v ref vout p vout n cs 1 16 16 1.0 mhz 1.0 mhz 8.0 khz 16-bit sigma-delta dac anti-imaging interpolation filter pga serial port high-pass digital filter analog smoothing filter digital sigma-delta modulator figure 1. ad28msp02 block diagram the iir low-pass filter is a 10th-order elliptic filter with a pass- band edge at 3.7 khz and a stopband attenuation of 65 db at 4 khz. this filter has the following specifications: filter type: 10th-order low-pass elliptic iir sample frequency: 40.0 khz passband cutoff:* 3.70 khz passband ripple: 0.2 db stopband cutoff: 4.0 khz stopband ripple: C65.00 db *the passband cutoff frequency is defined to be the last point in the passband that meets the passband ripple specification. (note that these specifications apply only to this filter, and not to the entire adc. the specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.) figure 2 shows the frequency response of the iir low-pass filter. 0 ?00 5000 ?0 2000 ?0 ?0 ?0 4400 3800 3200 2600 frequency ?hz log magnitude ?db figure 2. iir low-pass filter frequency response high-pass filter the digital high-pass filter removes frequency components at the low end of the spectrum; it attenuates signal energy below the passband of the converter. the high-pass filter can be bypassed by setting the adby bit (bit 3) of the ad28msp02s control register. the high-pass filter is a 4th-order elliptic filter with a passband cutoff at 150 hz. stopband attenuation is 25 db. this filter has the following specifications: filter type: 4th-order high-pass elliptic iir sample frequency: 8.0 khz passband cutoff: 150.0 hz passband ripple: 0.2 db stopband cutoff: 100.0 hz stopband ripple: C25.00 db (note that these specifications apply only to this filter, and not to the entire adc. the specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.) figure 3 shows the frequency response of the high-pass filter. 0 ?00 300 ?0 0 ?0 ?0 ?0 240 180 120 60 frequency ?hz log magnitude ?db figure 3. high-pass filter frequency response passband ripple is 0.2 db for the combined effects of the adcs digital filters (i.e., high-pass filter and iir low-pass of the decimation filter) in the 300 hzC3400 hz passband. the output of the adc is transferred to the ad28msp02s serial port (sport) at an 8 khz rate, for transmission to the host dsp processor. maximum group delay in the adc will not exceed 1 ms in the region from 300 hz to 3 khz.
ad28msp02 rev. 0 C3C d/a conversion the d/a conversion circuitry of the ad28msp02 consists of a sigma-delta digital-to-analog converter (dac), an analog smoothing filter, a programmable gain amplifier, and a differen- tial output amplifier. dac the ad28msp02s sigma-delta dac implements digital filters and a sigma-delta modulator with the same characteristics as the filters and modulator of the adc. the dac consists of a digital high-pass filter, an anti-imaging interpolation filter, and a digital sigma-delta modulator. the dac receives 16-bit samples from the host dsp processor via ad28msp02s serial port at an 8 khz rate. if the host pro- cessor fails to write a new value to the serial port, the existing (previous) data is read again. the data stream is filtered first by the dacs high-pass filter and then by the anti-imaging interpo- lation filter. these filters have the same characteristics as the adcs anti-aliasing decimation filter and digital high-pass filter. the output of the interpolation filter is fed to the dacs digital sigma-delta modulator, which converts the 16-bit data to 1-bit samples at a 1.0 mhz rate. the modulator noise-shapes the sig- nal such that errors inherent to the process are minimized in the passband of the converter. the bit stream output of the sigma- delta modulator is fed to the ad28msp02s analog smoothing filter where it is converted to an analog voltage. high-pass filter the digital high-pass filter of the ad28msp02s dac has the same characteristics as the high-pass filter of the adc. the high-pass filter removes frequency components at the low end of the spectrum; it attenuates signal energy below the passband of the converter. the dacs high-pass filter can be bypassed by setting the daby bit (bit 2) of the ad28msp02s control register. the high-pass filter is a 4th-order elliptic filter with a passband cutoff at 150 hz. stopband attenuation is 25 db. this filter has the following specifications: filter type: 4th-order high-pass elliptic iir sample frequency: 8.0 khz passband cutoff: 150.0 hz passband ripple: 0.2 db stopband cutoff: 100.0 hz stopband ripple: C25.00 db (note that these specifications apply only to this filter, and not to the entire dac. the specifications can be used to perform further analysis of the exact characteris- tics of the filter, for example using a digital filter design software package.) figure 3 shows the frequency response of the high-pass filter. interpolation filter the anti-imaging interpolation filter contains two stages. the first stage is an iir low-pass filter that interpolates the data rate from 8 khz to 40 khz and removes images produced by the in- terpolation process. the output of this stage is then interpolated to 1.0 mhz and fed to the second stage, a sinc 4 digital filter that attenuates images produced by the 40 khz to 1.0 mhz inter- polation process. pin descriptions pin name i/o/z function vin norm i analog input to inverting terminal of norm input amplifier. vfb norm o output terminal of norm amplifier. vin aux i analog input to inverting terminal of aux input amplifier. vfb aux o output terminal of aux amplifier. vout p o analog output from noninverting terminal of differential output ampl ifier. vout n o analog output from inverting terminal of differential output amplifier. v ref o on-chip bandgap voltage reference (2.5 v 10%). mclk i master clock input; frequency must equal 13.0 mhz to guarantee listed specifications. sclk o/z serial clock used to clock data or con trol bits to and from the serial port (sport). the frequency of sclk is equal to the frequency of the master clock (mclk) divided by 5. sclk is 3-stated when cs is low. sdi i serial data input of sport. both data and control information are input on this pin. input at sdi is ignored when cs is low. sdo o/z serial data output of sport. both data and control information are output on this pin. sdo is 3-stated when cs is low. sdifs i framing signal for sdi serial transfers. input at sdifs is ignored when cs is low. sdofs o/z f raming signal for sdo serial transfers. sdofs is 3-stated when cs is low. data/ cntrl i configures ad28msp02 for either data or control information transfers (via sport). cs i active-high chip select. can be used to 3-state the sport interface; when cs is low, the sclk, sdo, and sdofs outputs are 3-stated and the sdi and sdifs inputs are ignored. if cs is de- asserted during a serial data tran sfer, the 16-bit word being transmitted is lost. reset i active low reset signal; resets control register and clears digital filters. reset does not 3-state the sport outputs (sclk, sdo, sdofs). v cc analog supply voltage; nominal +5 v. gnd a analog ground. v dd digital supply voltage; nominal +5 v. gnd d digital ground.
ad28msp02 rev. 0 C4C the iir low-pass filter is a 10th-order elliptic filter with a pass- band edge at 3.70 khz and a stopband attenuation of 65 db at 4 khz. this filter has the following specifications: filter type: l0th-order low-pass elliptic iir sample frequency: 40.0 khz passband cutoff:* 3.70 khz passband ripple: 0.2 db stopband cutoff: 4.0 khz stopband ripple: C65.00 db *the passband cutoff frequency is defined to be the last point in the passband that meets the passband ripple specification. (note that these specifications apply only to this filter, and not to the entire dac. the specifications can be used to perform further analysis of the exact characteristics of the filter, for example using a digital filter design software package.) figure 2 shows the frequency response of the iir low-pass filter. passband ripple is 0.2 db for the combined effects of the dacs digital filters (i.e., high-pass filter and iir low pass of the interpolation filter) in the 300 hzC3400 hz passband. analog smoothing filter and programmable gain amplifier the programmable gain amplifier (pga) can be used to adjust the output signal level by C15 db to +6 db. this gain is selected by bits 7C9 (og0, og1, og2) of the ad28msp02s control register. the ad28msp02s analog smoothing filter consists of a 2nd- order sallen-key continuous-time filter and a 3rd-order switched capacitor filter. the sallen-key filter has a 3 db point at approximately 80 khz. differential output amplifier the ad28msp02s analog output (vout p , vout n ) is pro- duced by a differential output amplifier. the differential ampli- fier can drive loads of 2 k w or greater and has a maximum differential output voltage swing of 3.156 v peak-to-peak (3.17 dbm0). the output signal is dc-biased to the ad28msp02s on-chip voltage reference (v ref ) and can be ac-coupled directly to a load or dc-coupled to an external ampli- fier. refer to analog output in the design considerations section of this data sheet for more information. the vout p Cvout n outputs must be used as differential out- puts; do not use either as a single-ended output. serial port the ad28msp02 communicates with a host processor via the bidirectional synchronous serial port (sport). the sport is used to transmit and receive digital data and control inform ation. all serial transfers are 16 bits long, msb first. data bits are transferred at the serial clock rate (sclk). sclk equals the master clock frequency divided by 5. sclk = 2.6 mhz for the master clock frequency mclk = 13.0 mhz. host processor interface the ad28msp02-to-host processor interface is shown in fi gure 4. ad28msp02 sdo serial data receive sdofs receive frame sync sclk serial clock sdi serial data transmit sdifs transmit frame sync host processor data/cntrl flag figure 4. ad28msp02-to-host processor interface table i describes the sport signals and how they are used to communicate with the host processor. the ad28msp02s chip select (cs) must be held high to enable sport operation. cs can be used to 3-state the sport pins and disable communica- tion with the host processor. to use the adsp-2101 or adsp-2111 as host dsp processor for the ad28msp02, the following connections can be used (as shown in figure 5): ad28msp02 pin adsp-2101/2111 pin sclk C sclk0 sdo C dr0 sdofs C rfs0 sdi C dt0 sdifs C tfs0 data/ cntrl C fo (flag output) table i. sport signals signal signal state when signal state during name description generated by reset low (cs high) powerdown (cs high) sclk serial clock ad28msp02 low active sdo serial data output ad28msp02 low active* sdofs serial data output frame sync ad28msp02 low low sdi serial data input host processor sdifs serial data input frame sync host processor (cs must be held high to enable sport operation.) *outputs last data value that was valid prior to entering powerdown.
ad28msp02 rev. 0 C5C note that the adsp-2101s sport0 communicates with the ad28msp02s sport while the adsp-2101s flag output (fo) is used to signal the ad28msp02s data/ cntrl input. sport1 on the adsp-2101 must be configured for flags and interrupts in this system. figure 6 shows an adsp-2101 assembly language program that initializes the ad28msp02 and implements digital loopback through the dsp processor. sdo sdofs sclk data/cntrl sdi sdifs ad28msp02 dr0 rfs0 sclk0 fo dt0 tfs0 adsp-2101 figure 5. ad28msp02-to-adsp-2101 interface { this adsp-2101 program initializes the ad28msp02 } { and executes a loopback, or talk-through, routine. } .module/abs = 0/boot = 0 test1; resetv: jump begin; {restart} rti; rti; rti; irq2v: rti; rti; rti; rti; {irq2} st0x: rti; rti; rti; rti; {sport0 tx} sr0x: ax0 = rx0; {sport0 rx} tx0 = ax0; rti; rti; irq1v: rti; rti; rti; rti; {irq1} irq0v: rti; rti; rti; rti; {irq0} timerv: rti; rti; rti; rti; begin: reset flag out; ax0 = 0x2a0f; {configure adsp-2101 sport0 for } dm (0x3ff6) = ax0; { ext. sclk, ext. rfs, int. tfs } ax0 = 0x101f; { enable adsp-2101 sport0, } dm (0x3fff) = ax0; { configure sport1 for flag out } imask= 0x10; ax0 = 0x30; { write control word to take} tx0 = ax0; { ad28msp02 out of powerdown } idle; nop; imask= 0x08; set flag out; wait: jump wait; { wait for receive interrupt } nop; .endmod; figure 6. adsp-2101 digital loopback routine
ad28msp02 rev. 0 C6C gain og2 og1 og0 +6 db 0 0 0 +3 db 0 0 1 0 db 0 1 0 C3 db 0 1 1 C6 db 1 0 0 C9 db 1 0 1 C12 db 1 1 0 C15 db 1 1 1 gain settings are accurate within 0.6 db. (control register is set to 0x0000 at reset. reserved bits 10C15 must be set to 0 for all control register writes.) table ii. control word write format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 og2 og1 og0 0 pwdd pwda adby daby ims ips serial data output the ad28msp02s sport will begin transmitting data to the host processor at an 8 khz rate when the pwdd and pwda bits (bits 4, 5) of the control register are set to 1. in the pro- gram shown in figure 6, the instructions ax0 = 0x30; { write control word to take } tx0 = ax0; { ad28msp02 out of powerdown } accomplish this by writing 0x30 to the ad28msp02s control register. there is a short start-up time (after the end of this con- trol register write) before the ad28msp02 raises sdofs and begins transmitting data; see figure 11. at the 13 mhz mclk frequency, data is transmitted at an 8 khz rate with a single 16-bit word transmitted every 125 m s. while data is being output, the ad28msp02 asserts sdofs at an 8 khz rate. each 16-bit word transfer begins one serial clock cycle after sdofs is asserted. serial data input the host processor must initiate data transfers to the ad28msp02 by asserting the serial data input frame sync (sdifs) high. the 16-bit word transfer begins one serial clock cycle after sdifs is asserted. the data/cntrl line must be driven high when sdifs is driven high. the host processor must assert sdifs shortly after the rising edge of sclk and must maintain sdifs high for one cycle. data is then driven from the host processor (to the sdi input) shortly after the rising edge of the next sclk and is clocked into the ad28msp02 on the falling edge of sclk in that cycle. each bit of a 16-bit data word is thus clocked into the ad28msp02 on the falling edge of sclk (msb first). if sdifs is asserted high again before the end of the present data word transfer, it is not recognized until the falling edge of sclk in the last (lsb) cycle. (note: exact sport timing requirements are defined in the specifications section of this data sheet.) control register the ad28msp02s control register configures the device for various modes of operation including adc and dac gain set- tings, adc input mux selection, filter bypass, and powerdown. the ad28msp02s host processor can read and write to the control register through the ad28msp02s serial port (sport) by driving the data/ cntrl pin low. the control register is cleared (set to 0x0000) when the ad28msp02 is reset. control register writes to write the control register, the host processor must assert data/ cntrl low when it asserts sdifs. if the msb of the bit stream is also low, the sport recognizes the incoming serial data as a new control word and copies it to the ad28msp02s control register. the format for the control word write is shown in table ii; reserved bits 10-15 must be set to zero. 0 ips analog input preamplifier select: 1 = insert (+20 db), 0 = bypass (0 db) 1 ims analog input multiplexer select: 1 = aux input, 0 = norm input 2 daby dac high-pass filter bypass select: 0 = insert, 1 = bypass 3 adby adc high-pass filter bypass select: 0 = insert, 1 = bypass 4 pwda powerdown analog: 0 = powerdown, 1 = operating 5 pwdd powerdown digital: 0 = powerdown, 1 = operating 7C9 og2-og0 analog output gain setting (for d/a output pga) 10C15 reserved
ad28msp02 rev. 0 C7C table iii. control word read format read request 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100 0 0 0 00 0 00 0 0 000 read ready 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 110 0 0 0 00 0 00 0 0 000 control register reads to read the control register, the host processor must transfer two control words. for each transfer, the data/ cntrl pin must be low when sdifs is asserted. if the msb of the bit stream is high, the sport recognizes the incoming serial data as a request for control information. the protocol for reading the control register is as follows: 1. the host processor sends a read request control word to the ad28msp02. since the msb of this control word is high, the sport recognized the incoming serial data as a read re- quest and does not overwrite the control register. 2. when the ad28msp02 receives the read request, it finishes any data transfers in progress and waits for a read ready control word. 3. the host processor then transfers a read ready control word to the ad28msp02. upon receiving this control word, the ad28msp02 transfers the control register contents to the host processor via the sport. 4. when the sport completes the control register transfer, it immediately resumes transmitting data at an 8 khz rate. this scheme allows any data transfers in progress to be com- pleted and resolves any ambiguities between data and control words. the format for the read control words is shown in table iii. design considerations analog input the analog input signal to the ad28msp02 must be ac-coupled. figure 7 shows the recommended input circuit for the ad28msp02s analog input pin (either vin norm or vin aux ). the circuit of figure 7 implements a first-order low-pass filter with a 3 db point at 20 khz; this is the only filter that must be implemented external to the ad28msp02 to prevent aliasing of the sampled signal. since the ad28msp02s adc uses a highly oversampled approach that transfers the bulk of the anti-aliasing filtering into the digital domain, the off-chip anti-aliasing filter need only be of low order. in the circuit shown in figure 7, scaling of the analog input is achieved by the resistors r in and r fb . the input signal gain, Cr fb /r in , can be adjusted from C12 db to +26 db by varying the values of these resistors. the ad28msp02s on-chip 20 db preamplifier can be enabled when there is not enough gain in the input circuit; the preamplifier is configured by bit 0 (ips) of the control register. total gain must be configured to ensure that a full-scale input signal (at c in in figure 7) produces a sig- nal level at the input to the sigma-delta modulator of the adc that does not exceed v inmax , which is specified under analog interface electrical characteristics. if the total gain is increased above unity, signal-to-noise (snr + thd) performance will not meet the listed specifications. mux voltage reference vfb vfb vin ad28msp02 vin norm aux norm aux c fb c in r in r fb input signal figure 7. recommended analog input circuit the dc biasing of the analog input signal is accomplished with an on-chip voltage reference which nominally equals 2.5 v. the input signal must be ac-coupled with an external coupling ca- pacitor (c in ). c in and r in should be chosen to ensure a cou- pling corner frequency of 30 hz. c in should be 0.1 m f or larger.
ad28msp02 rev. 0 C8C to select values for the components shown in figure 7, use the following equations: gain = r fb r in c in = 1 60 p r in c fb = 1 (2 p )( 20 10 3 ) r fb 10 k w r fb , r in 50 k w 150 pf c fb 600 pf figure 8 shows an example of a typical input circuit configured for 0 db gain. the circuits diodes are used to prevent the input signal from exceeding maximum limits. 1.0? 330pf input signal v cc gnd a mux voltage reference vfb aux vin aux ad28msp02 20k w 10k w 10k w vfb norm vin norm figure 8. example analog input circuit for 0 db gain analog output the ad28msp0 2s differential analog output (vout p , vout n ) is produced by an on-chip differential amplifier. the differential amplifier can drive a minimum load of 2 k w (r l 3 2 k w ) and has a maximum differential output voltage swing of 3.156 v peak-to-peak (3.17 dbm0). the differential output can be ac-coupled directly to a load or dc-coupled to an external amplifier. figure 9 shows a simple circuit providing a differential output with ac coupling. the capacitor of this circuit (c out ) is optional; if used, its value can be chosen as follows: c out = 1 (60 p ) r l c out c out vout p vout n r l ad28msp02 figure 9. example circuit for differential output the vout p Cvout n outputs must be used as differential out- puts; do not use either as a single-ended output. figure 10 shows an example circuit which can be used to convert the dif- ferential output to a single-ended output. the circuit uses a differential-to-single-ended amplifier, the analog devices ssm2141. ssm2141 1 5 7 4 +12 v 0.1 m f 0.1 m f ?2 v v out ad28msp02 vout p vout n gnd a gnd a gnd a figure 10. example circuit for single-ended output
ad28msp02 rev. 0 C9C serial output startup time the ad28msp02 begins transmitting data to the host processor after it is taken out of powerdown. to take the ad28msp02 out of powerdown, the host processor writes a control word to the ad28msp02. the start-up time (from the start of this control word write) before the ad28msp02 begins transmitting data is shown in figure 11. pc board layout considerations separate analog and digital ground planes should be provided for the ad28msp02 in order to ensure the characteristics of the devices adc and dac. the two ground planes should be con- nected at a single pointthis is often referred to as a star or mecca grounding configuration. the point of connection may be at the system power supply, at the pc board power connec- tion, or at any other appropriate location. because ground loops increase susceptibility to emf, multiple connections between the analog and digital ground planes should be avoided. the ground planes should be designed such that all noise- sensitive areas are isolated from one another and critical signal traces (such as digital clocks and analog signals) are as short as possible. each +5 v digital supply pin, v dd , of the ad28msp02 (soic pins 20, 21) should be bypassed to ground with a 0.1 m f capaci- tor. these capacitors should be low inductance, monolithic, ce- ramic, and surface-mount. the capacitor leads and pc board traces should be as short as possible to minimize inductive ef- fects. in addition, a 10 m f capacitor should be connected be- tween v dd and ground, near the pc board power connection. mclk frequency the sigma-delta converters and digital filters of the ad28msp02 are specifically designed to operate at a master clock (mclk) frequency of 13.0 mhz. mclk must equal 13.0 mhz to guar- antee the filter characteristics and sample rate of the adc and dac. the ad28msp02 is not tested or characterized at any other clock frequency. a low cost crystal with a different frequency, for example 12.288 mhz, can be used for the master clock input; in this case, however, the ad28msp02 is not guaranteed to meet the specifications listed in this data sheet. sdo first data word transmitted from ad28msp02 sclk data/ cntrl sdifs sdofs msb 410 sclk cycles (2050 mclk cycles) sdi msb powerup control word written to ad28msp02 2nd msb 2nd msb figure 11. serial output startup time
ad28msp02 rev. 0 C10C definition of specifications absolute gain absolute gain is a measure of converter gain for a known signal. absolute gain is measured with a 1.0 khz sine wave at 0 dbm0. the absolute gain specification is used as a reference for gain tracking error specification. gain tracking error gain tracking error measures changes in converter output for different signal levels relative to an absolute signal level. the ab- solute signal level is 1 khz at 0 dbm0 (equal to absolute gain). gain tracking error at 0 dbm0 is 0 db by definition. snr + thd signal-to-noise ratio plus total harmonic distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components in the frequency range 300 hzC3400 hz, including harmonics but excluding dc. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m or n are equal to zero. for final testing, the second or- der terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb), and (fa C 2fb). idle channel noise idle channel noise is defined as the total signal energy measured at the output of the device when the input is grounded (mea- sured in the frequency range 300 hzC3400 hz). crosstalk crosstalk is defined as the ratio of the amplitude of a full-scale signal appearing on one channel to the amplitude of the same signal which couples onto the adjacent channel. crosstalk is ex- pressed in db. power supply rejection power supply rejection measures the susceptibility of a device to noise on the power supply. power supply rejection is measured by modulating the power supply with a sine wave and measuring the noise at the output (relative to 0 db). group delay group delay is defined as the derivative of radian phase with re- spect to radian frequency, ?f(w) / ?w . group delay is a measure of average delay of a system as a function of frequency. a linear system with a constant group delay has a linear phase response. the deviation of group delay away from a constant indicates the degree of nonlinear phase response of the system.
ad28msp02 rev. 0 C11C specifications recommended operating conditions k grade b grade parameter min max min max unit v dd , v cc supply voltage 4.50 5.50 4.50 5.50 v t amb ambient operating temperature 0 +70 C40 +85 c refer to environmental conditions for information on case temperature and thermal specifications. absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v input voltage . . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C55 c to +150 c lead temperature (5 sec) soic . . . . . . . . . . . . . . . . . +280 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity the ad28msp02 features proprietary input protection circuitry to dissipate high-energy discharges (human body model). per method 3015 of mil-std-883c, the ad28msp02 has been classified as a class 1 device. proper esd precautions are strongly recommended to avoid functional damage or performance degradation. charges readily accumulate on the human body and test equipment and discharge without detection. unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. warning! esd sensitive device
ad28msp02 rev. 0 C12C digital interface electrical characteristics symbol parameter min typ max unit test condition v ih input high voltage 2.4 v v dd = max v il input low voltage 0.8 v v dd = min v oh output high voltage 2.4 v v dd = min, i oh = C0.5 ma v ol output low voltage 0.4 v v dd = min, i ol = 2 ma i ih high level input current 10 m av dd = max, v in = max i il low level input current 10 m av dd = max, v in = 0 v i ozl low level output 3-state leakage current 10 m av dd = max, v in = max i ozh high level output 3-state leakage current 10 m av dd = max, v in = 0 v c i digital input capacitance 10 pf analog interface electrical characteristics symbol parameter min typ max unit adc: i l input leakage current at vin norm , vin aux 10 na r i input resistance 1 at vin norm , vin aux 100 m w c il input load capacitance 1 at vin norm , vin aux 10 pf vin max maximum input range 2 3.156 v p-p dac: r o output resistance 1, 3 1 w v ooff output dc offset 4 400 mv c ol output load capacitance 3 100 pf v vref voltage reference (v ref ) 2.25 2.75 v v o maximum voltage output swing (p-p) across r l single-ended 3.156 v differential 6.312 v r l load resistance 3 2k w test conditions for all analog interface tests: unity input gain, a/d 20 db preamplifier bypassed, d/a pga set for 0 db gain, no load on analog output (vout p Cvout n ). 1 guaranteed but not tested. 2 at input to sigma-delta modulator of adc. 3 at vout p -vout n . 4 between vout p and vout n . power dissipation symbol parameter min max unit v cc analog operating voltage 4.5 5.5 v v dd digital operating voltage 4.5 5.5 v i dd operating current active 1 40 ma p 1 power dissipation active 1 200 mw i dd operating current inactive 2 0.5 ma p 0 power dissipation inactive 2 2.5 mw test conditions: v dd = v cc = 5.0 v, mclk frequency 13.0 mhz, no load on digital pins, analog inputs ac-coupled to ground, no load on analog output (vout p Cvout n ) i active: ad28msp02 operational (pwdd and pwda set to 1 in control register). 2 inactive: ad28msp02 in powerdown state (pwdd and pwda set to 0 in control register) and mclk tied to v dd .
ad28msp02 rev. 0 C13C timing parameters clock signals parameter min max unit timing requiremen t: t mck mclk period 76.9 76.9 ns t mkl mclk width low 0.5t mck C 10 0.5t mck + 10 ns t mkh mclk width high 0.5t mck C 10 0.5t mck + 10 ns switching characteristic : t sck sclk period 5t mck ns t skl sclk width low 3t mck C 10 3t mck + 10 ns t skh sclk width high 2t mck C 10 2t mck + 10 ns mclk sclk t mck t mkl t mkh a a a t sck t skl t skh a a a a a a a a a a a a a a figure 12. clock signals serial port 3-state parameter min max unit switching characteristic : t spd cs low to sdo, sdofs, sclk disable 25 ns t spe cs high to sdo, sdofs, sclk enable 0 ns t spv cs high to sdo, sdofs, sclk valid 10 ns cs a a a a a a a a a a a a a a a a a a a a sdo sdofs sclk t spd t spe t spv figure 13. serial port 3-state
ad28msp02 rev. 0 C14C serial ports parameter min max unit timing requirements: t scs sdi/sdifs setup before sclk low 10 ns t sch sdi/sdifs hold after sclk low 10 ns t dcs data/ cntrl setup before sclk low 10 ns t dch data/ cntrl hold after sclk low 10 ns switching characteristic: t rd sdofs delay from sclk high 15 ns t rh sdofs hold after sclk high 0 ns t scdh sdo hold after sclk high 0 ns t scdd sdo delay from sclk high 30 ns sclk sdifs a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a data/cntrl a a a a a a a sdi a a t sck t scs t sch a a t dcs a a a a t dch t sch a a msb 2nd msb 3rd msb t scs a a sdofs t rd t rh t scdd t scdh a a a a a sdo a a a figure 14. serial ports
ad28msp02 rev. 0 C15C digital test conditions 3.0v 1.5v 0.0v 2.0v 1.5v 0.8v digital input digital output figure 15. volt age reference levels for ac measurements to digital output pin 50pf +1.5v i oh i ol figure 16. equivalent device loading for ac measurements (includes all fixtures) gain parameter min typ max unit test conditions adc absolute gain C0.2 0 0.2 dbm0 1.0 khz, 0 dbm0 adc gain tracking error C0.1 0 0.1 dbm0 1.0 khz, +3 to C50 dbm0 dac absolute gain C0.2 0 0.2 dbm0 1.0 khz, 0 dbm0 dac gain tracking error C0.1 0 0.1 dbm0 1.0 khz, +3 to C50 dbm0 frequency response input freq min output max output (hz) (db) (db) 0C C25 100 C C25 150 C0.3 +0.3 200 C0.3 +0.3 300 C0.2 +0.2 1000 C0.2 +0.2 2000 C0.2 +0.2 3000 C0.2 +0.2 3400 C0.2 +0.2 3700 C0.3 +0.3 4000 C C60 >4000 C C60 frequency responses of adc and dac measured with input at audio reference level (the input level that produces an output level of C10 dbm0), with 20 db preamplifier bypassed and input gain of 0 db. the in-band ripple shall not ex- ceed 0.2 db.
ad28msp02 rev. 0 C16C noise and distortion parameter min max unit test conditions adc intermodulation distortion C70 db dac intermodulation distortion C70 db adc idle channel noise 72 dbm0 dac idle channel noise 72 dbm0 adc crosstalk C65 db adc input signal level: 1.0 khz, 0 dbm0 dac input at idle dac crosstalk C65 db adc input signal level: analog ground dac output signal level: 1.0 khz, 0 dbm0 adc power supply rejection C55 db input signal level at v cc and v dd pins: 1.0 khz, 100 mv p-p sine wave dac power supply rejection 55 db input signal level at v cc and v dd pins: 1.0 khz, 100 mv p-p sine wave adc group delay 1 1 ms 300C3000 hz dac group delay 1 1 ms 300C3000 hz 1 guaranteed but not tested. 70 ?0 10 0 30 20 40 50 60 3.17 ?5 ?0 0 ? ?0 ?5 ?5 ?0 ?5 ?0 ?5 ?0 ?0 v ?dbm0 in snr+thd ?db figure 17. snr + thd vs. v in ordering guide part temperature package number range package option* ad28msp02kn 0 c to +70 c 24-pin plastic dip n-24 ad28msp02kr 0 c to +70 c 28-lead soic r-28 AD28MSP02BN C40 c to +85 c 24-pin plastic dip n-24 ad28msp02br C40 c to +85 c 28-lead soic r-28 *n = plastic dip, r = small outline (soic).
ad28msp02 rev. 0 C17C pin configurations 24-pin plastic dip 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 ad28msp02 v cc v ref vout p vout n gnd a gnd d data/cntrl sdo sdofs sdi sdifs sclk vin norm vfb norm vin aux vfb aux gnd a nc nc reset cs mclk nc = no connection 13 14 gnd d v dd top view (not to scale) 28-lead soic 1 2 3 4 5 6 7 8 9 10 11 12 28 15 16 17 18 19 20 21 22 23 24 ad28msp02 v cc v ref vout p vout n gnd a gnd d data/cntrl sdo sdofs sdi sdifs sclk vin norm vfb norm vin aux vfb aux gnd a gnd d v dd nc nc reset cs mclk nc = no connection 13 26 14 25 27 gnd d gnd a gnd d v dd top view (not to scale)
ad28msp02 rev. 0 C18C outline dimensions dimensions shown in inches and (mm). 24-pin plastic dip (n-24) 0.210 (5.33) max 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc pin 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) seating plane 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 1.275 (32.30) 1.125 (28.60) 0.280 (7.11) 0.240 (6.10) 24 1 13 12 28-lead wide-body soic (r-28) pin 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 28 15 14 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.1043 (2.65) 0.0926 (2.35) 0.7125 (18.10) 0.6969 (17.70) 0.0118 (0.30) 0.0040 (0.10)
C19C
c1672C8C6/92 printed in u.s.a. C20C

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